/******************************************************************************

 Copyright (c) 1999 Advanced Micro Devices, Inc.

 LIMITATION OF LIABILITY:  THE MATERIALS ARE PROVIDED *AS IS* WITHOUT ANY
 EXPRESS OR IMPLIED WARRANTY OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY,
 NONINFRINGEMENT OF THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY
 PARTICULAR PURPOSE.  IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY
 DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
 BUSINESS INTERRUPTION, LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
 INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY
 OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION OR LIMITATION
 OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE LIMITATION MAY
 NOT APPLY TO YOU.

 AMD does not assume any responsibility for any errors which may appear in the
 Materials nor any responsibility to support or update the Materials.  AMD retains
 the right to make changes to its test specifications at any time, without notice.

 NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
 further information, software, technical information, know-how, or show-how
 available to you.

 So that all may benefit from your experience, please report  any  problems
 or  suggestions about this software to 3dsdk.support@amd.com

 AMD Developer Technologies, M/S 585
 Advanced Micro Devices, Inc.
 5900 E. Ben White Blvd.
 Austin, TX 78741
 3dsdk.support@amd.com

*****************************************************************************

 ADETECT.H

 AMD3D 3D library code: CPU Feature detection

*****************************************************************************/

#ifndef _AMD_DETECT_H
#define _AMD_DETECT_H

// Detected CPU Vendors - returned by GetCPUCaps (CPU_VENDOR_STRING);
typedef enum CPU_VENDORS
{
    VENDOR_UNKNOWN,
    VENDOR_AMD,
    VENDOR_INTEL,
    VENDOR_CYRIX,
    VENDOR_CENTAUR,
    VENDOR_NEXGEN,
    VENDOR_UMC,
    VENDOR_RISE,
    VENDOR_TRANSMETA
} CPU_VENDORS;

// Detected CPU models - returned by GetCPUCaps (CPU_TYPE);
typedef enum CPU_TYPES
{
    UNKNOWN,
    AMD_Am486,
    AMD_5x86,
    AMD_5K86,
    AMD_K5,
    AMD_K6,
    AMD_K6_2,
    AMD_K6_3,
    AMD_ATHLON,
    AMD_ATHLON4,
    AMD_ATHLON_MP,
    AMD_ATHLON_XP,
    AMD_DURON,

    INTEL_486DX,
    INTEL_486SX,
    INTEL_Pentium,
    INTEL_Pentium_MMX,
    INTEL_Pentium_Pro,
    INTEL_Pentium_II,
    INTEL_Pentium_II_Klamath,
    INTEL_Pentium_II_Deschutes,
    INTEL_Pentium_II_Mobile,
    INTEL_Celeron,
    INTEL_Celeron_Covington,
    INTEL_Celeron_Mendocino,
    INTEL_Pentium_III,
    INTEL_Pentium_III_Katmai,
    INTEL_Pentium_III_Coppermine,
    INTEL_Pentium_III_Tualatin,
    INTEL_Pentium_III_Mobile,
    INTEL_Pentium_III_Xeon,
    INTEL_Pentium_IV,
    INTEL_Pentium_IV_Mobile,
    INTEL_Pentium_Xeon,

    CYRIX_MediaGX,
    CYRIX_5x86,
    CYRIX_6x86,
    CYRIX_MediaGXm,
    CYRIX_6x86MX,

    UMC_U5D,
    UMC_U5S,

    CENTAUR_IDTC6,
    CENTAUR_IDTC2,

    VIA_SAMUEL1,
    VIA_SAMUEL2,
    VIA_EZRA
} CPU_TYPES;


// Detected CPU capabilities - used as input to the GetCPUCaps() function
typedef enum CPUCAPS
{
    // Synthesized values
    CPU_VENDOR,         // Manufacturer (returns enum CPU_VENDORS)
    CPU_TYPE,           // CPU type (return enum CPU_TYPES)
    CPU_VENDOR_STRING,  // CPU vendor name string (return const char *)
    CPU_NAME_STRING,    // CPU Processor string (extended functions 0x80000002 - 0x80000004, return const char *)
    CPU_VENDOR_LOGO,    // CPU vendor logo number

    // Processor Features - returned as boolean values
    HAS_CPUID,          // Supports CPUID instruction
    HAS_FPU,            // FPU present
    HAS_VME,            // Virtual Mode Extensions
    HAS_DEBUG,          // Debug extensions
    HAS_PSE,            // Page Size Extensions
    HAS_TSC,            // Time Stamp Counter
    HAS_MSR,            // Model Specific Registers
    HAS_PAE,            // Page Address Extensions
    HAS_MCE,            // Machine Check Extensions
    HAS_CMPXCHG8,       // CMPXCHG8 instruction
    HAS_APIC,           // APIC
    HAS_SYSENTER,       // SYSENTER/SYSEXIT instruction
    HAS_MTRR,           // Memory Type Range Registers
    HAS_GPE,            // Global Paging Extensions
    HAS_MCA,            // Machine Check Architecture
    HAS_CMOV,           // CMOV instruction
    HAS_PAT,            // Page Attribue Table
    HAS_PSE36,          // PSE36 (Page Size Extensions)
    HAS_PSN,            // PSN (96-bit Processor Serial Number)

    HAS_EMMX,           // MMX Extensions
    HAS_MMX,            // MMX support
    HAS_FXSR,           // FXSAVE/FXRSTOR instruction

    HAS_3DNOW_EXT,      // Extended 3DNow! support
    HAS_3DNOW,          // 3DNow! support

    HAS_SSE_MMX,        // SSE MMX support (same as HAS_EMMX)
    HAS_SSE,            // SSE
    HAS_SSE_FP,         // SSE FP support
    HAS_SSE2,           // SSE2
    HAS_AMD_MP,         // AMD Multiprocessing Capable

    // Cache parameters (not all values apply to all cpus)
    CPU_L1_DTLB_ASSOC,      // L1 Data Cache TLB Associativity
    CPU_L1_DTLB_ENTRIES,    // L1 Data Cache TLB Entries
    CPU_L1_ITLB_ASSOC,      // L1 Instruction Cache TLB Associativity (0xff = full associativity)
    CPU_L1_ITLB_ENTRIES,    // L1 Instruction Cache TLB Entries

    CPU_L1_EDTLB_ASSOC,     // Extended (2/4 Mbyte) L1 Data Cache TLB Associativity (0xff = full associativity)
    CPU_L1_EDTLB_ENTRIES,   // Extended (2/4 Mbyte) L1 Data Cache TLB Entries
    CPU_L1_EITLB_ASSOC,     // Extended (2/4 Mbyte) L1 Instruction Cache TLB Associativity
    CPU_L1_EITLB_ENTRIES,   // Extended (2/4 Mbyte) L1 Instruction Cache TLB Entries

    CPU_L1_DCACHE_SIZE,     // L1 Data Cache Size (kbytes)
    CPU_L1_DCACHE_ASSOC,    // L1 Data Cache Associativity (0xff = full associativity)
    CPU_L1_DCACHE_LINES,    // L1 Data Cache Lines
    CPU_L1_DCACHE_LSIZE,    // L1 Data Cache Line Size (bytes)

    CPU_L1_ICACHE_SIZE,     // L1 Instruction Cache Size (kbytes)
    CPU_L1_ICACHE_ASSOC,    // L1 Instruction Cache Associativity (0xff = full associativity)
    CPU_L1_ICACHE_LINES,    // L1 Instruction Cache Lines
    CPU_L1_ICACHE_LSIZE,    // L1 Instruction Cache Line Size (bytes)

    CPU_L2_CACHE_SIZE,      // L2 Unified Cache Size (Kbytes)
    CPU_L2_CACHE_ASSOC,     // L2 Unified Cache Associativity (0xf = full associativity)
    CPU_L2_CACHE_LINES,     // L2 Unified Cache Lines (lines per tag)
    CPU_L2_CACHE_LSIZE,     // L2 Unified Cache Line Size (bytes)

    CPU_L2_DTLB_ASSOC,      // L2 Data Cache TLB Associativity
    CPU_L2_DTLB_ENTRIES,    // L2 Data Cache TLB Entries
    CPU_L2_UTLB_ASSOC,      // L2 Instruction or Unified Cache TLB Associativity (0xf = full associativity)
    CPU_L2_UTLB_ENTRIES,    // L2 Instruction or Unified Cache TLB Entries

    CPU_L2_EDTLB_ASSOC,     // Extended (2/4 Mbyte) L2 Data Cache TLB Associativity (0xf = full associativity)
    CPU_L2_EDTLB_ENTRIES,   // Extended (2/4 Mbyte) L2 Data Cache TLB Entries
    CPU_L2_EUTLB_ASSOC,     // Extended (2/4 Mbyte) L2 Instruction or Unified Cache TLB Associativity
    CPU_L2_EUTLB_ENTRIES,   // Extended (2/4 Mbyte) L2 Instruction or Unified Cache TLB Entries

} CPUCAPS;

#endif // _AMD_DETECT_H
